U.S. Pat. No. 5,640,398 "State Machine Architecture for Concurrent Processing of Multiplexed Data Streams" (hereafter "the '398 patent") describes the architecture shown in FIG. 1, in which a pipelined state machine coupled to a state vector stored in a random access memory ("RAM") enables concurrent processing of a number of data channels. The '398 patent makes no mention of how data in RAM 12 is to be initialised at system start up, or updated by a control processor. Typically, the RAM entry pertaining to a particular channel includes data such as option selection codes which determine how the state machine is to process that channel's data stream. Such data may need to be updated or observed by a control processor from time to time.
A simple method of providing control processor access to RAM 12 is to provide an additional data port on RAM 12. For example, if the state machine uses separate read and write ports to access RAM 12, then a triple-port RAM may be used instead of a dual-port RAM, with the third port being reserved for control processor access. However, this method suffers from the disadvantage that multi-port memories are more complex and expensive due to the requirement to replicate address decode circuitry and re-design the memory bit cells.
A second method is to multiplex access to RAM 12's write port between the state machine and the control processor. When the control processor wishes to update the RAM entry corresponding to a particular channel, a multiplexer examines the stream of write addresses being generated by state machine pipeline 18 and, when the required address is present at RAM 12's write port, substitutes the data supplied by the control processor for the state machine's write data. However, this method is feasible only if Timing Generator and Control block 10 is able to generate all possible RAM addresses within a reasonable time, so that the multiplexer is not forced to wait indefinitely for an address match. In certain systems (for example, if channels are permitted to have widely differing data rates, or if channels may be disabled for extended periods), it may not be possible to satisfy this condition. The '398 patent describes the operation of the state machine in a SONET application in which Timing Generator and Control block 10 tracks SONET time slots and cycles through all RAM addresses periodically, thereby satisfying the foregoing condition.
The present invention improves upon the architecture of the '398 patent in a manner which facilitates timely control processor or other hardware access to RAM 12 without requiring an additional RAM port; and, which can be used in situations in which Timing Generator and Control block 10 is unable to generate every RAM address within a predeterminable time frame. The invention also facilitates control processor access to any state machine RAM location, even if that location is not within the address space of Timing Generator and Control block 10. In prior art SONET applications, state machine RAMs are indexed by SONET time slot, with Timing Generator and Control block 10 cycling through all RAM addresses. However, in Internet PPP applications in which data is transported in HDLC format over channelised T1 or E1 links, state machine RAMs are indexed by HDLC channel, and it is possible for a single channel to be mapped to one or more time slots of a TDM link. Accordingly, in a HDLC application, it may be necessary to initialise a channel's RAM entry before that entry is mapped to a time slot. If a channel is unmapped, Timing Generator and Control block 10 will not generate the RAM address for that channel's entry, if configured in accordance with the '398 patent.